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ICs for Consumer Electronics
Single Chip PIP System SDA 9288X (A141) PIP 2
Data Sheet 03.96
Edition 03.96 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SDA 9288X Revision History: Previous Version: Page (in previous Version) Page (in new Version)
Current Version: 03.96 Subjects (major changes since last revision)
25.1.1994: 22; 23; 24 24 25 26 32 35 43 19; 21 43 15 20; 25 23 All 10; 15; 18 15; 19 17 17 22 25 28; 29 30 32 25.1.1994: 25.1.1994: 25.1.1994: 25.1.1994: 25.1.1994: 25.1.1994: 25.1.1994: 19.4.1994: 19.4.1994: 20.6.1994: 20.6.1994: 20.6.1994: 18.7.1994: 18.7.1994: 18.7.1994: 18.7.1994: 18.7.1994: 18.7.1994: 18.7.1994: 18.7.1994: 18.7.1994: 18.7.1994:
Preliminary Specification V1.1 warnings additional bits VSIISQ, VSPISQ at subad. 07/08 additional bits DACONDE, DACONST at subad. 0D supply voltage range values DAC diagram influence HSIDEL to VSIDEL adjustment additional note PLL switch READ27 timing of ADC clamping warning subaddr. 02 additional bit SELDOWN at subaddr. 0B value
VOL outputs SEL, SELD added
pages no. shifted improvement: additional bits D5, D6 (CLPS; CLPFIX) at subaddr. 06 bit D0 of subaddress 0D deleted new: examples for adjustment of frame colors text bits IMOD, PMOD additional remark at subaddress 02 clamping current. Additional values application board layout and application circuit new timing of ADC clamping changed values DAC output current
SDA 9288X
Table of Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 3 3.1 3.2 3.3 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.3 4.3.1 4.3.2 5 I2C Bus
Page
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Conversion, Inset Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIP Field Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Matrix Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DA Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Receiver Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Current of DA Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Voltage Generation for ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adjustment of YDEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three Level Interface (3-L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Board Layout Proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuit (R, G, B-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing of ADC Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Relation of Sync Pulses at Frame Mode . . . . . . . . . . . . . . . . . . . . . . 12 12 13 14 16 17 17 17 18 18 18 18 18 19 25 25 26 31 34 34 35 35 38 39 40 41 42 42 43
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips.
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1
General Description
The Picture-in-Picture Processor SDA 9288X A141 generates a picture of reduced size of a video signal (inset channel) for the purpose of combining it with another video signal (parent channel). The easy implementation of the IC in an existing system needs only a few additional external components. There is a great variety of application facilities in professional and consumer products (TV sets, supervising monitors, multi-media, ...)
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Single Chip PIP System
SDA 9288X
Data Sheet 1.1 Features
MOS
* Single chip solution Clamping, AD conversion, filtering, field memory, RGB matrix, DA-conversion and clock generation integrated on one chip * 2 picture sizes 1/9 or 1/16 of normal size P-DSO-32-2 * High resolution display 13.5 MHz/27 MHz display clock frequency 212 luminance and 53 chrominance pixels per inset line for picture size 1/9 6-bit amplitude resolution for each incoming signal component Field and frame mode display Horizontal and vertical filtering Special antialias filtering for the luminance signal * 16:9 compatibility Operation in 4:3 and 16:9 sets 4:3 inset signals on 16:9 displays or v.v. with picture size 1/9 and 1/16, respectively * Analog inputs Y, + (B-Y), + (R-Y) or Y, -(B-Y), -(R-Y) * Analog outputs Y, + (B-Y), + (R-Y) or Y, - (B-Y), - (R-Y) or RGB 3 RGB matrices: EBU, NTSC (Japan), NTSC (USA) * Free programmable position of inset picture Steps of 1 pixel and 1 line All PIP and POP positions are possible * Programmable framing 4096 frame colors Variable frame width
Type SDA 9288X
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Ordering Code on request
6
Package P-DSO-32-2
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* Freeze picture * I2C Bus control * Threefold PIP/POP facility Three different I2C-addresses (pin-programmable) Tri-State outputs * Numerical PLL circuit for high stability clock generation * No necessity of PAL/SECAM delay lines (using suitable color decoders i.e. TDA 8310) * Multistandard applications 625 lines/525 lines standard (inset and parent channel) Scan conversion systems as flickerfree display systems (parent channel) HDTV (parent channel) * P-DSO-32-2 package/350 mil (SMD) * 5 V supply voltage
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1.2
Pin Configuration (top view)
P-DSO-32-2
Figure 1
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1.3
Pin Definitions and Functions Function1) Descriptions S I I Analog voltage supply (VSS) for ADC Lower reference voltage for AD converters Quartz oscillator (input) or quartz clock (from another PIP IC) or line locked clock (27 MHz, from a digital parent channel) Quartz oscillator (output) Digital voltage supply (VDD) Analog voltage supply (VSS) for DAC and PLL Analog output: chrominance signal + (R-Y) or - (R-Y) or R Analog output: luminance signal Y or G Analog output: chrominance signal + (B-Y) or - (B-Y) or B Analog voltage supply (VDD) for DAC and PLL Reference current for DA-converters Single frequency fast PIP switching output (tristate) Double frequency fast PIP switching output (tristate) Capacitor connection for smoothing internally generated substrate bias I2C Bus address control Digital voltage supply (VSS) Multifrequency vertical sync for parent channel Multifrequency horizontal sync for parent channel Double frequency vertical sync for parent channel or vertical sync input for inset channel Double frequency horizontal sync for parent channel or horizontal sync input for inset channel I2C Bus data I2C Bus clock I2C Bus controlled output1 I2C Bus controlled output2
Pin No. Symbol 1 2 3
VSSA1 VREFL
XIN
4 5 6 7 8 9 10 11 12 13 14 15 16,27 17 18 19 20 21 22 23 24
1)
XQ
Q S S Q/ana Q/ana Q/ana S Q/ana Q Q S I3-L S I I I
VDD VSSA2
OUT1 OUT2 OUT3
VDDA2 IREF
SEL SELD
VBB
ADR
VSS
VP HP/SCP VPD/VI
HPD/SCI I SDA SCL SW1 SW2 I/Q I Q3-L Q3-L
I : input, Q : output, ana : analog, TTL : digital (TTL), 3-L : 3-level, S : supply voltage
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1.3
Pin Definitions and Functions (cont'd) Function1) Descriptions I3-L I3-L Special 3-level hor. and vert. sync signal for inset channel Input for standard depending internal switching (LOW (L) = PAL, MID (M) = NTSC, HIGH (H) = SECAM) Analog input: luminance signal Y Analog voltage supply (VDD) for ADC Analog input: chrominance signal + (B-Y) or - (B-Y) Upper reference voltage for AD converters Analog input: chrominance signal + (R-Y) or - (R-Y)
Pin No. Symbol 25 26 HVI SYS
28 29 30 31 32
YIN VDDA1 UIN VREFH VIN
I/ana S I/ana I I/ana
I : input, Q : output, ana : analog, TTL : digital (TTL), 3-L : 3-level, S : supply voltage
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1.4
Functional Block Diagram
Figure 2
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2 2.1
System Description AD Conversion, Inset Synchronization
The inset video signal is fed to the SDA 9288X A141 as analog luminance and chrominance components1). The polarity of the chrominance signals is programmable. After clamping the video components are AD-converted with an amplitude resolution of 6 bit. The conversion is done using a 13.5 MHz clock for the luminance signal and a 3.375 MHz clock for the chrominance signals. For the adaption to different application the clamp timing for the analog inputs can be chosen (CLPS; CLPFIX). Setting this bits to `1' can be useful for non-standard input signals. For inset synchronization it is possible to feed either a special 3-level signal via pin HVI (detection of horizontal and vertical pulses) or separate signals via pins SCI for horizontal and VI for vertical synchronization. SCI is the horizontal synchron signal of the inset channel. If the burst gate pulse of the sandcastle is used it must be adapted to TTL compatible levels by a simple external circuit. Centering of the displayed picture area is possible by a programmable delay for the horizontal synchronization signal (HSIDEL). The inset horizontal synchronization signals are sampled with 27 MHz. This 27 MHz clock and the AD converter clocks are derived from the parent horizontal synchronization pulse (see chapter 2.6) or from the quartz frequency converted by a factor of 4/3. Delay differences between luminance and chrominance signals at the input of the IC caused by chroma decoding are compensated by a programmable luminance delay line (YDEL) of about - 290 ns ... 740 ns (at decimation input; see Application Information). By analyzing the synchronization pulses the line standard of the inset signal source is detected and interference noise on the vertical sync signal is removed. For applications with fixed line standard (only 625 lines or 525 lines) the automatic detection can be switched off. The phase of the vertical sync pulse is programmable (VSIDEL; VSPDEL). By this way a correct detection of the field number is possible, an important condition for frame mode display.
Note: The adjustment of VSIDEL is influenced by HSIDEL (see chapter 4.3), vertical synchronization via pin HVI causes an additional internal delay for the vertical sync pulse of about 16 s.
1)
To improve the signal-to-noise ratio the amplitude of the input signals should be as large as possible.
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2.2
Input Signal Processing
This stage performs the decimation of the inset signal by horizontal and vertical filtering and sub-sampling. A special antialias filter improves the frequency response of the luminance channel. It is optimized for the use of the horizontal decimation factor 3:1. A window signal, derived from the sync pulses and the detected line standard, defines the part of the active video area used for decimation. For HSIDEL = `0' the decimation window is opened about 104 clock periods (13.5 MHz) after the horizontal synchronization pulse. For the 625 lines standard the 36th video line is the first decimated line, for the 525 lines standard decimation starts in the 26th video line. The following filters are implemented: Horizontal Decimation 3:1 3:1 4:1 4:1 Vertical Decimation 3:1 3:1 4:1 4:1 Component Luminance Chrominance Luminance Chrominance Component Luminance Chrominance Luminance Chrominance Filter 1 + z - 1 + z- 2 1 + 2 x z- 1 + z- 2 1 + z - 1 + z- 2 + z- 3 1 + z - 1 + z- 2 + z- 3 Filter 1 + z- L + z- 2L 1 + 2 x z- L + z- 2L 1 + z- L + z- 2L+ z- 3L 1 + z- L + z- 2L+ z- 3L
z = ejT,T = 1/13.5 MHz for luminance T = 1/3.375 MHz for chrominance L = samples per line for luminance respectively chrominance
The realized chrominance filtering allows omitting the color decoder delay line for PAL and SECAM demodulation if the color decoder supplies the same output voltages independent of the kind of operation. In case of SECAM signals an amplification of the chrominance signals by a factor of 2 is necessary because just every second line a signal is present. This chrominance amplification is programmable via pin SYS or I2C Bus (AMSEC). The horizontal and vertical decimation factors are free programmable (DECHOR, DECVER). Using different decimations horizontal and vertical 16:9 applications become realizable: DECHOR = `1', DECVER = `0': picture size 1/9 for 4:3 inset signals on 16:9 displays DECHOR = `0', DECVER = `1': picture size 1/16 for 16:9 inset signals on 4:3 displays
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2.3
PIP Field Memory
The on-chip memory stores one decimated field of the inset picture. Its capacity is 169 812 bits. The picture size depends on the horizontal and vertical decimation factors. Horizontal Decimation Y 3:1 4:1 Vertical Decimation 3:1 3:1 4:1 4:1 212 160 Line Standard 625 525 625 525 PIP PIXELS per Line (B-Y) 53 40 (R-Y) 53 40 PIP Lines 88 76 66 57
In field mode display just every second inset field is written into the memory, in frame mode display the memory is continuously written. Data are written with the lower inset clock frequency depending on the horizontal decimation factor (4.5 MHz or 3.375 MHz). Normally the read frequency is 13.5 MHz and 27 MHz for scan conversion systems. For progressive scan conversion systems and HDTV displays a line doubling mode is available (LINEDBL). Every line of the inset picture is read twice. Memory writing can be stopped by program (FREEZE), a freeze picture display results (one field). Having no scan conversion and the same line numbers in inset and parent channel (625 lines or 525 lines both) frame mode display is possible. The result is a higher vertical and time resolution because of displaying every incoming field. For this purpose the standards are internally analysed and activating of frame mode display is blocked automatically when the described restrictions are not fulfilled. As in the inset channel a field number detection is carried out for the parent channel. Depending on the phase between inset and parent signals a correction of the display raster for the read out data is performed by omitting or inserting lines when the read address counter outruns the write address counter. The display position of the inset picture is free programmable (POSHOR, POSVER). The first possible picture position (without frame) is 54 clock periods (13.5 MHz or 27 MHz) after the horizontal and 4 lines after the vertical synchronization pulses. Starting at this position the picture can be moved over the whole display area. Even POP-positions (Picture Outside Picture) at 16:9 applications are possible.
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Having different line standards in inset and parent channels we have a so called mixed mode display. It causes deformations in the aspect ratio of the inset picture. A special mixed mode display is available for the picture size 1/9 (MIXDIS): - Parent channel 625 lines, inset channel 525 lines: The inset picture is shifted down by 6 lines. By performing this shifting the centers of the inset pictures have the same position for both line standards. - Parent channel 525 lines, inset channel 625 lines: The inset picture gets a reduced line number of 76. The first and the last 6 lines are omitted. This way the inset picture size is the same as for 525 lines inset signals. The display shows the center part of the original picture. Synchronization of memory reading with the parent channel is achieved by processing the parent horizontal and vertical synchronization signals in the same way as described for the inset channel. The synchronization signals are fed to the IC at pin HP/SCP for horizontal synchronization and pin VP for vertical synchronization. In the same way as described for the inset channel the burst gate of the sandcastle signal can be used for horizontal synchronization. In scan conversion systems also the inputs HPD/SCI and VPD/VI are available if the input HVI is activated for inset synchronization.
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2.4
Output Signal Processing
At the memory output the chrominance components are demultiplexed and linearly interpolated to the luminance sample rate. Different output formats are available: luminance signal Y with inverted or non-inverted chrominance signals (B-Y), (R-Y) or RGB. For the RGB conversion 3 matrices are integrated: Standard EBU NTSC (Japan) NTSC (USA) B-Y 1 1 1 R-Y 0.558 0.783 1.013 G-Y 0.345 0.31 0.305 B-Y 0 0 0 R-Y 90 95 104 G-Y 237 240 252
Matrix selection is done by pin SYS or I2C Bus. The matrices are designed for the following input voltages (100 % white, 75 % color saturation): Component Y B-Y R-Y Input Voltage (without sync) in % of Full Scale Input Range of ADC 75 100 100
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2.4.1
Matrix Equations EBU
R G= B
1 0 1 0 0.78125 1 - 0.1875 - 0.40625 1
B-Y R-Y Y
NTSC (Japan)
R G= B
1 0 1 - 0.0625 1.09375 1 - 0.15625 - 0.375 1
B-Y R-Y Y
NTSC (USA)
R G B
=
1 0 1 B-Y - 0.25 1.375 1 R - Y - 0.09375 - 0.40625 1 Y
2.4.2
Frame Insertion
A colored frame is added to the inset picture. 4096 frame colors are programmable, 4 bits for each component Y, (B-Y), (R-Y) (bits FRY, FRU, FRV). The horizontal and
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vertical width of the frame are independently programmable. Width = 0 means display without frame. Examples for the Adjustment of Frame Colors
Frame Color Blue Green White Red Yellow Cyan FRY FRU FRV D3 ... D0 of Subaddress 09 D3 ... D0 of Subaddress 0A D7 ... D4 of Subaddress 0A 0100 0100 1100 0100 1100 1100 0110 1000 0000 1000 1000 0010 0110 1010 1010 0000 0111 0100 1010 0100
Magenta 0100
2.4.3
Select Signal
For controlling an external switch (for example an RGB processor) a select signal is supplied. Pin SEL is active in normal 13.5 MHz reading mode, pin SELD is active using 27 MHz. The phases of these signals are programmable for adaption to different external output signal processing.
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2.5
DA Conversion
The SDA 9288X A141 includes three 6-bit DA converters. Each converter supplies a current through an external resistor that is connected between VSSA and OUT1, OUT2, OUT3 respectively. The current is controlled by a digital control circuit. Each command DACONST or PIPON starts the adjustment cycle. 2.6 PLL
A numerical PLL circuit supplies a clock of about 27 MHz with high stability. The generated clock is locked to the parent horizontal synchronization pulse. Its frequency depends linearly on the frequency of the sync signal and the quartz frequency. The recommended quartz frequencies are listed under `Recommended Operation Conditions'. Using up to three SDA 9288X A141 ICs in one application only a single quartz is necessary. Four time constants are programmable via I2C Bus. If the PLL is switched off an external 27 MHz parent line locked clock can be fed to the IC. The inset clock generation is possible in two ways: 1. Synchron with the parent horizontal synchronization pulse (bit CLISW = `0') 2. Synchron with the quartz frequency (bit CLISW = `1'; fcli = 4/3 x fquartz). In this mode the aspect ratio is independent on the parent sync frequency but depends on the used resonator type. It is only possible to use one of the two modes.
Note: Before setting bit D3 of subaddress 00 (READ27) noise reduction of the VSP pulse must be switched off (D5 of subaddress 08 = `1').
2.7 2.7.1 I2C Bus I2C Bus Addresses
Three different I2C addresses are programmable via pin ADR. Pin ADR Low level (VSS or VSSA) Mid level (open) High level (VDD or VDDA) 2.7.2 S Address (bin.) 11010110 11011100 11011110 Address (hex.) D6 DC DE
I2C Bus Receiver Format Address A Subaddress A Data Byte A **** AP
S: start condition A: acknowledge P: stop condition Only write operation is possible. An automatically address increment function is implemented.
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2.7.3
Subaddr. Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D D7 0 0
I2C Bus Commands
Data Bytes D6 SYSACT SELDEL3 D5 FREEZE SELDEL2 D4 PLLOFF SELDEL1 D3 READ27 SELDEL0 D2 LINEDBL MIXDIS D1 FRAME D0 PIPON
POSHOR9 POSHOR8
POSHOR7 POSHOR6 POSHOR5 POSHOR4 POSHOR3 POSHOR2 POSHOR1 POSHOR0 POSVER7 0 DECVER 0 AMSEC POSVER6 SW21 DECHOR CLPS 0 POSVER5 SW20 INSHVI CLPFIX VSIISQ VSPISQ CON1 FRV3 POSVER4 SW11 CHRINS CLISW VSIDEL4 VSPDEL4 CON0 FRV2 POSVER3 SW10 PMOD1 HSIDEL3 VSIDEL3 VSPDEL3 FRY5 FRU5 FRWIDV0 MAT1 0 POSVER2 YDEL2 PMOD0 HSIDEL2 VSIDEL2 VSPDEL2 FRY4 FRU4 FRWIDH2 MAT0 0 POSVER1 YDEL1 IMOD1 HSIDEL1 VSIDEL1 VSPDEL1 FRY3 FRU3 FRWIDH1 CHRPIP 0 POSVER0 YDEL0 IMOD0 HSIDEL0 VSIDEL0 VSPDEL0 FRY2 FRU2 FRWIDH0 OUTFOR 0
PARSYND 0 CON3 FRV5 0 0 CON2 FRV4 0 0
SELDOWN FRWIDV1 0 PLLTC2 MAT2 0
DACONST PLLTC1
After switching on the IC the data bytes of all registers are set to `0', the bit PLLOFF is set to `1'.
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Bit
Name
Function
Subaddress 00 D0 D1 PIPON FRAME 0: PIP insertion OFF 1: PIP insertion ON 0: field display 1: frame display (under special restrictions). Correct adjustment of bits VSIDEL, VSPDEL required (see chapter 4.3) 0: each line of the PIP memory is read once (normal operation) 1: each line of the PIP memory is read twice (line doubling for progressive scan conversion systems in parent channel) 0: PIP display with single read frequency (13.5 MHz) 1: PIP display with double read frequency (27 MHz) (see note page 19). 0: internal PLL ON 1: internal PLL OFF (external clock generation) 0: live picture 1: freeze picture 0: pin SYS inactive: selection of decimation amplification and RGB-matrix is done via I2C Bus 1: pin SYS active: selection of decimation amplification and RGB-matrix is done via pin SYS
D2
LINEDBL
D3
READ27
D4 D5 D6
PLLOFF FREEZE SYSACT
Subaddress 01 D1 ... D0 POSHOR D2 MIXDIS 2 MSBs of POSHOR (see also subaddress 02) 0: PIP picture height depends just upon inset line standard, position upon POSHOR 1: modified PIP picture height and position for different inset and parent line standards (mixed display mode) Delay of output signal SELECT at pins SEL respectively SELD (- 8 ... 7 periods of read frequency clock, programmable in 2's complement code). SELDEL = `0': SELECT signal has the same phase as the PIP picture signal referenced to the IC output.
D6 ... D3 SELDEL
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Bit
Name
Function
Subaddress 02 D7 ... D0 POSHOR Horizontal position of PIP picture (raster: 1 pixel) Note: The 2 MSBs of POSHOR are located at subaddress 01 Warning: It is not allowed to adjust positions < 2 and > 740. Note: To avoid horizontal jumping of the picture by changing POSHOR from `00 1111 1111' to `01 0000 0000' its necessary to transfer the bits of both subaddresses during the same field period. Subaddress 03 D7 ... D0 POSVER Vertical position of PIP picture (raster: 1 line) Warning: It is not allowed to adjust positions > 220 (50 Hz) or > 182 (60 Hz).
Subaddress 04 D2 ... D0 YDEL Delay of luminance input signal 000: minimum delay 111: maximum delay; see chapter 4.2 Direct control of output pin SW1 (3 levels) 00: low level 01: mid level 10: high level 11: high level Direct control of output pin SW2 (3 levels) 00: low level 01: mid level 10: high level 11: high level
D4 ... D3 SW1
D6 ... D5 SW2
Semiconductor Group
22
03.96
SDA 9288X
Bit
Name
Function
Subaddress 05 D1 ... D0 IMOD 00: 01: 10: 11: 00: 01: 10: 11: automatic detection of line standard (inset signal) fixed adjustment 625 lines1) fixed adjustment 525 lines1) freeze last line standard automatic detection of line standard (parent signal) fixed adjustment 625 lines1) fixed adjustment 525 lines1) freeze last line standard
D3 ... D2 PMOD
D4 D5
CHRINS INSHVI
0: chrominance input signals + (B-Y), + (R-Y) 1: inverted chrominance input signals - (B-Y), - (R-Y) 0: inset synchronization signals via pins HPD/SCI and VPD/VI 1: inset synchr. signals via pin HVI (3-I. sand-castle signal) 0: horizontal decimation 3 to 1 1: horizontal decimation 4 to 1 0: vertical decimation 3 to 1 1: vertical decimation 4 to 1
D6 D7
DECHOR DECVER
Subaddress 06 D3 ... D0 HSIDEL Delay of horizontal synchronization pulse (inset signal) Raster: 6 clock periods of 13.5 MHz. Warning: Adjustment of HSIDEL will influence the adjustment of VSIDEL (subaddr. 07); see chapter 4.3 0: inset clock synchronized with parent clock 1: inset clock synchronized with quartz frequency Note: Only one of the two modes can be used. Switching back from `1' to `0' is not possible! 0: clamp pulses of ADC are dependent on the adjustment of HSIDEL 1: clamp pulses fixed; no influence of HSIDEL 0: three clamp cycles per line (timing see diagram) 1: two clamp cycles per line
D4
CLISW
D5
CLPFIX
D6
1)
CLPS
Fixed adjustments for IMOD and PMOD result in undefined working conditions when signal standards are used which are different from the programmed values.
Semiconductor Group
23
03.96
SDA 9288X
Bit
Name
Function
Subaddress 07 D4 ... D0 VSIDEL Delay of vertical synchronization pulse (inset signal) in steps of 2.37 s. Warning: Correct adjustment value is influenced by the adjustment of HSIDEL (subaddr. 06); see chapter 4.3. Noise reduction of the VSI pulse (set to `0' under normal conditions) 0: unity amplification of decimation filters (normal mode) 1: amplification by a factor of 2 (SECAM signals without delay line in the chroma decoder)
D5 D7
VSIISQ AMSEC
Subaddress 08 D4 ... D0 VSPDEL D5 VSPISQ Delay of vertical synchronization pulse (parent signal) in steps of 2.37 s/1.68 s (50/100 Hz) Noise reduction of the VSP pulse (should be set to `0' under normal conditions); in case changing from standard mode to line or frame conversion modes `1' should be set during the changement of line frequency
D7
PARSYND 0: parent synchronization signals for double frequency read via pins HP/SCP and VP 1: parent synchronization signals for double frequency read via pins HPD/SCI and VPD/VI (INSHVI = `1' required)
Subaddress 09 D3 ... D0 FRY D7 ... D4 CON Luminance component of frame color (4 MSBs of 6 bit) Contrast adjustment of PIP picture; steps and adjustment range depending on the external output resistors. Proposed value see chapter 3.3
Subaddress 0A D3 ... D0 FRU D7 ... D4 FRV Chrominance component (B-Y) of frame color (4 MSBs of 6 bit) Chrominance component (R-Y) of frame color (4 MSBs of 6 bit)
24 03.96
Semiconductor Group
SDA 9288X
Bit
Name
Function
Subaddress 0B D2 ... D0 FRWIDH D4 ... D3 FRWIDV D5 Horizontal width of PIP frame (0 ... 7 pixels) Vertical width of PIP frame (0 ... 3 lines)
SELDOWN 0: open source output at pins SEL, SELD 1: TTL output at pins SEL, SELD
Subaddress 0C D0 D1 D2 D3 D4 OUTFOR CHRPIP MAT0 MAT1 MAT2 0: format of output signals: Y, (B-Y), (R-Y) 1: format of output signals: R G B 0: chrominance output signals: + (B-Y), + (R-Y) 1: inverted chrominance output signals: - (B-Y), - (R-Y) 0: EBU RGB-matrix 1: NTSC RGB-matrix 0: preselection of NTSC RGB matrix (USA) 1: preselection of NTSC RBG matrix (Japan) 0: matrix selection by bit MAT0 1: automatic matrix selection depending on inset line standard
Subaddress 0D D0 D5 DACONDE Set to `0' PLLTC2 Time constant of internal PLL: 00: medium damping, low resonance frequency 01: medium damping, high resonance frequency 10: high damping, low resonance frequency 11: high damping, high resonance frequency Note: After power ON PLLTC must remain at 00 until the system is locked.
D6
PLLTC1
D7
DACONST Changing from `0' to `1' starts automatic adjustment of OUT1 ... 3 output current (switching PIPON gives the same result).
Semiconductor Group
25
03.96
SDA 9288X
3 3.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. 70 125 125 260 - 0.5 V VDD + 0.5 V -1 7 - 0.5 V VDD + 0.5 V -1 -1 - 0.25 - 100 7 7 0.25 900 100 C C C C 1 V 1 Duration < 10 s Analog inputs (YIN, UIN, VIN, IREF) All other pins Pins OUT1, OUT2, OUT3, XQ, SW1, SW2 All other pins 0 - 55 Unit Remark
Parameter Ambient temperature Storage temperature Junction temperature Soldering temperature Input voltage
TA Tstg Tj TSOLD VI VI VQ
Output voltage
VQ Supply voltages VDD Supply voltage differentials VDD D Total power dissipation Ptot
Latch-up protection
V V V mW mA
Except pins OUT1, OUT2, OUT3, IREF, XQ, XQ, YIN, UIN, VIN
Note: All voltages listed are referenced to ground (0 V, VSS) except where noted. Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Semiconductor Group
26
03.96
SDA 9288X
3.2
Operational Range Symbol min. 4.75 0 Limit Values typ. 5 25 max. 5.5 70 V C Unit Remark
Parameter Supply voltages
VDDxx Ambient temperature TA
All TTL Inputs Low-level input voltage High-level input voltage
VIL VIH
-1 2.0
0.8 6
V V
All Three Level Inputs (3-L) (see figure) High-level input voltage Low-level input voltage
VIH VIL
3.5 -1
6 0.8
V V Open input, see chapter 3.3
Medium-level voltage VIM
All 3-L Outputs (see figure) High-level output current Low-level output current
IOH IOL
- 500 0
0 1.6
A mA
Inset Horizontal Sync TTL and 3-L Inputs: HPD/SCI, HVI1) Horizontal frequency Signal rise time Signal high time Signal medium or low time
1)
14.53
16.72 100
kHz ns ns ns Noisefree L/M-to-H transition
100 900
All values are referred to the corresponding min (VIH), max (VIM) and max (VIL)
Semiconductor Group
27
03.96
SDA 9288X
3.2
Operational Range (cont'd) Symbol min. Limit Values typ. max. Unit Remark
Parameter
Inset Vertical Sync TTL and 3-L Inputs: VPD/VI, HVI1) Signal medium or high time Signal low time 17 200 s ns Necessary for vertical sync detection
Parent Horizontal Sync TTL Inputs: HP/SCP, HPD/SCI2) Sync frequency in single frequency display mode Sync frequency in double frequency display mode Signal rise time Signal high time Signal low time 100 900 14.53 15 29.06 30 16.72 17.19 33.44 kHz kHz kHz Quartz frequency 20.480 MHz Quartz frequency 21.090 MHz Quartz frequency 20.480 MHz Quartz frequency 21.090 MHz Noisefree transition
34.375 kHz 100 ns ns ns
Parent Vertical Sync TTL Input VDP/VI2) Signal HIGH time Signal LOW time
1) 2)
200 200
ns ns
All values are referred to the corresponding min (VIH), max (VIM) and max (VIL) All values are referred to the corresponding min (VIH) and max (VIL)
Semiconductor Group
28
03.96
SDA 9288X
3.2
Operational Range (cont'd) Symbol min. Limit Values typ. max. Unit Remark
Parameter
Quartz/Ceramic Resonator2) Recommended frequency Series resistance 20.25 20.48 21.3 10 20 30 40 MHz 21.09 MHz for MUSE
C1, C2 33 pF C1, C2 22 pF C1, C2 15 pF C1, C2 10 pF
(total series capacitance)
Optional TTL Clock Input: XIN1) Clock input cycle time Clock input rise time Clock input fall time Clock input low time Clock input high time Fast I2C Bus1) 3) SCL clock frequency Inactive time before start of transmission Setup time start condition Hold time start condition SCL low time
1) 2)
35
40 5 5
ns ns ns ns ns
External line locked; 27 MHz clock (I2C: internal PLL OFF)
10 10
fSCL tBUF tSU; STA tHD; STA tLOW
0 1.3 0.6 0.6 1.3
400
kHz s s s s
All values are referred to min (VIH) and max (VIL). There is no internal protection for the crystal driver against oscillation at harmonic frequencies. 3) This specification of the bus lines does not have to be identical with the I/O stages specification because of optional series resistors between bus lines and I/O pins.
Semiconductor Group
29
03.96
SDA 9288X
3.2
Operational Range (cont'd) Symbol min. Limit Values typ. max. s ns 0.9 300 s ns s 400 pF $ = 0.1Cb/pF 0.6 100 0 20 + $ 0.6 Unit Remark
Parameter SCL high time Setup time data Hold time data SDA/SCL rise/fall times Setup time stop condition Capacitive load/bus line
tHIGH tSU; DAT tHD;DAT tR, tF tSU; STO Cb
I2C Bus Inputs/Output: SDA, SCL High-level input voltage Low-level input voltage Spike duration at inputs Low-level output current
VIH VIL
3 - 0.5 0 0
VDD
+ 0.5 1.5 50 6
V V ns mA
Also for SDA/SCL input stages
IOL
Analog to Digital Converters (6 bit) Input coupling capacitors Y, U, V source resistance Reference voltage low Reference voltage high Reference voltage difference 10 100 1 nF k V V V Min and max values only with optional external resistors, see also chapter 3.3. Necessary for proper clamping
VREFL VREFH VREFH - VREFL
0.5 1.5 0.5
1.0 2.0 1.0
1.5 2.5 2
Semiconductor Group
30
03.96
SDA 9288X
3.2
Operational Range (cont'd) Symbol min. Limit Values typ. max. Unit Remark
Parameter
Digital-to-Analog Converters (6 bit) Full range output voltage
VOFR
4.2
1 5.1
2 6.3
V k
Peak to peak Bits CON = `0000'; no contrast adjustment used Contrast adjustment via I2C Bus
Reference resistance RREF1
RREF2
6.0
6.8
7.5
k
Note: In the operational range the functions given in the circuit description are fulfilled.
Semiconductor Group
31
03.96
SDA 9288X
3.3
Characteristics Symbol Limit Values Unit Remark min. max. 160 120 40 20 mA mA mA mA
Parameter Average total supply current
IDDtot Average digital supply current IDD Average analog supply current IDDA1 Average analog supply current IDDA2
All Digital Inputs (TTL, I2C) Input capacitance Input leakage current
IDDtot = IDD + IDDA1+ IDDA2
Note: The maxima do not necessarily coincide.
CI
- 10
7 10
pF A
Not tested Including leakage current of SDA output stage
All Three Level Inputs (3-L) (see figure) Input capacitance Medium-level open input voltage Differential input resistance SEL, SELD High-level output voltage High-level output voltage Low-level output voltage Leakage current Output capacitance All 3-L Outputs High-level output voltage High-level output voltage Low-level output voltage
CI VIM RIN
7 2.1 8 2.5 14
pF V k
Not tested |IIN| 1 A, VDD = 5 V Not tested
VOH VOH VOL
2.4 V VDD 1.5 V VDD 0.4 - 10 7
V V V A pF
IOH = - 200 A IOH = - 4.5 mA IOL = 1.6 mA, only valid
if bit SELDOWN = `1'
VO = 0 V ... VDD
Not tested
VOH VOH VOL
4 3.9 0.4
V V V
IOH = - 100 A IOH = - 500 A IOL = max
Semiconductor Group
32
03.96
SDA 9288X
3.3
Characteristics (cont'd) Symbol Limit Values Unit Remark min. max. 1 7 A pF Tristate Not tested
Parameter Medium-level output leakage current Output capacitance I2C Inputs: SDA/SCL Schmitt trigger hysteresis
IOM
-1
Vhys
0.2
V
Not tested
I2C Input/Output: SDA (referenced to SCL; open drain output) Low-level output voltage Low-level output voltage Output fall time from min (VIH) to max (VIL)
VOL VOL tOF
0.4 0.6 20 + 250 0.1 x Cb/pF - 100 100 7 -1 1 50 90 150 1.02
V V ns
IOL = 3 mA IOL = max 10 pF Cb 400 pF
Analog-to-Digital Converters (6 bit) Y, U, V input leakage current Y, U, V input capitance Input clamping error Input clamping current |ICLP| 15 40 70 0.98 nA pF A A A V Not tested Deviation < 1 LSB Deviation 1 ... 2 LSB Deviation > 2 LSB LSB Settled state
Reference voltage difference
VREFH - VREFL
VDDA = nom, (VREFH - VREFL VDDA1/5)
Digital-to-Analog Converters (6 bit): Current Source Outputs OUT1, OUT2, OUT31) D.C. differential nonlinearity Full range output current DNLE - 0.5 - 1.4 2 0.5 - 1.7 3 LSB RREF = 5.1 k mA
IO
VDDA = max, TA = nom, RREF = 5.1 k, RL = 680 ,
after adjustment
Semiconductor Group
33
03.96
SDA 9288X
3.3
Characteristics (cont'd) Symbol Limit Values Unit Remark min. max. 1.18 V
Parameter Output voltage (VON 1.6 x VDDA x RL/RREF)
VO
0.96
VDDA = max, TA = nom, RL = 680 , RREF = 5.1 k,
after adjustment
Tracking
-3
3
%
Contrast increase
30
%
VDDA = max, TA = nom, RREF = 5.1 k, RL = 680 VDDA = nom, TA = nom, RL = 680 , RREF = 6.8 k,
contrast bits change from `0000' to `1111' for typical values see chapter 4
Supply voltage dependence of DAC output current Temperature dependence of DAC output current Dependence of DAC output current on external reference resistor
1) I2C:
For typical values see chapter 4 For typical values see chapter 4 For typical values see chapter 4
Contrast bits set to zero unless otherwise noted.
Note: The listed characteristics are ensured over the operating range of the integrated circuit unless restricted to nominal operating conditions (all voltages refer to VSS). The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
Semiconductor Group
34
03.96
SDA 9288X
4 4.1
Diagrams Output Current of DA Converters
Nominal values: VDDA = 5 V; VREF = 5.1 k; T = 25 C Measurements after adjustment via bit d7 of I2C Bus address 0D for each step
Note: The output currents are controlled in digital way, so inaccuracy of 1 LSB (ca. 2 %) is always possible.
Output current = f (VDDA) Output current = f (TA)
Semiconductor Group
35
03.96
SDA 9288X
Output current = f (RREF)
Current = f (CON 0 ... 3)
Semiconductor Group
36
03.96
SDA 9288X
4.2 4.2.1
Application Information Reference Voltage Generation for ADC
Figure 3 Signal Input Range 1 Vpp at Y, U, V
Figure 4 Signal Input Range 2 Vpp at Y, U, V
Semiconductor Group 37 03.96
SDA 9288X
Figure 5 Signal Input Range 0.5 Vpp at Y, U, V
Semiconductor Group
38
03.96
SDA 9288X
4.2.2
Adjustment of YDEL
Figure 6
Semiconductor Group
39
03.96
SDA 9288X
4.2.3
Three Level Interface (3-L)
Figure 7 High level (H): Medium level (M): Low level (L): upper transistor ON, lower transistor OFF both transistors OFF (interface voltage determined by input stage) upper transistor OFF, lower transistor ON
Semiconductor Group
40
03.96
SDA 9288X
4.2.4
Application Board Layout Proposal
Figure 8 (top view)
Figure 9 (bottom view)
Semiconductor Group 41 03.96
SDA 9288X
4.2.5
Application Circuit (R, G, B-mode)
Figure 10
Semiconductor Group
42
03.96
SDA 9288X
4.3 4.3.1
Waveforms Timing of ADC Clamping
Figure 11 The values are valid if HSIDEL = `0'. To get the maximum values 444 ns for each step of HSIDEL adjustment must be added (CLPFIX = `0'). With CLPFIX = `1' there is no influence of the HSIDEL adjustment to the clamp timing.
Semiconductor Group 43 03.96
SDA 9288X
4.3.2
Phase Relation of Sync Pulses at Frame Mode
If the phase relation is not correct at the H and V sync inputs, an adjustment via bits VSIDEL and VSPDEL is possible.
Figure 12 Signal Flow of the Horizontal Synchronization (insert part)
Figure 13 Allowed Phase Relation of the Horizontal/Vertical Sync Pulses (insert channel) if VSIDEL(0:4) = `0000'
Semiconductor Group 44 03.96
SDA 9288X
Figure 14 Allowed Phase Relation of the Horizontal/Vertical Sync Pulses (parent channel)if VSIDEL(0:4) = `0000'
Semiconductor Group
45
03.96
SDA 9288X
5
Package Outlines P-DSO-32-2 (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 46
Dimensions in mm
03.96
GPS05697

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